1. Field of the Invention
The present invention relates to power-controlled computer systems. More particularly, the present invention relates to power-conserving circuits and methods in computer systems with power control functionality.
2. Description of the Related Art
A power event is generated by a device in a computer system. Power events are generated by various devices that support a power interface such as an Advanced Configuration and Power Interface (ACPI), ranging from processors and controllers to many other devices with a wide range of complexity and sophistication. Power events include fixed ACPI events and general-purpose events. Fixed ACPI events include: (1) setting of a carry-bit of a power management timer, (2) actuation of a power button, (3) actuation of a sleep button, (4) a realtime clock (RTC) alarm wakeup, (5) setting of a wake status bit, (6) receipt of a system bus master request, and (7) raising of a global release status. General purpose events include various conditions designated to generate an event signal upon occurrence. General purpose events include wake events, a dispatching event for servicing an ACPI-aware device driver, and a queuing event for determining a control method to queue for execution. The device generating the power event signals the event via a network link to a server. ACPI events are typically signaled by a System Control Interrupt (SCI).
The ACPI specification defines four CPU power states as follows:
C0: The CPU is in a fully operational state. PA1 C1: The CPU is in a halted state, having executed a halt instruction and awaiting an interrupt. PA1 C2: The CPU is in a "stop grant" state, a low power state in which the CPU cache can still be snooped. PA1 C3: The CPU is in a "stop clock" state, a low power state such that the CPU's cache cannot be snooped.
The ACPI specifies that the CPU is to consume less power in state C3 than in state C2, that the CPU is to consume less power in state C2 than in state C1, and that the CPU is to consume less power in state C1 than in state C0. The C0 state is a fully-operational state in which the processor is supported by a full-power expenditure. In a typical system, the CPU power consumption in the C2 state is about 10% of the power consumption in the C0 state. The power consumption in the C3 state is about one to two percent of the power consumption of C0 state. Power consumption differences of these magnitudes are typically very important in portable systems that have a charge lifetime that depends on the conservation of battery power.
During the operation of a computer system, when a PCI bus cycle transfers a request for access of system memory, a snoop of the CPU cache is typically necessary for several reasons. The snoop prevents the cycle from accessing invalid data, data that is only valid in the cache. The snoop also prevents cache data from being "old" or "obsolete" due to the fact that the system memory copy of the data has been updated by the PCI cycle.
The C2 state is defined as a "snoopable" state so that, for an access to system memory, monitoring is allowed to determine whether the data targeted by the access is in-fact within the CPU cache. Knowledge of which pieces of information reside in the CPU caches and system memories is important to ensure that only valid data, and not data which is obsolete, is accessed, All information is valid with respect to the CPU. However, the memory and caches may be accessed via various devices and buses that bypass the CPU. For example, a device on a PCI bus may attempt to access system memory without determining whether updated versions of the data reside in an internal CPU cache. Eventually, some data corresponding to information that has been changed in the CPU cache will be accessed by the device so that incorrect data is obtained. Accordingly, every access to system memory is "snooped" by accessing the corresponding data in the processor cache.
However, a problem is raised in the C3 state or "non-snoopable" state since power is conserved in the C3 state by disabling the timing CPU clock signals to the CPU so that the CPU is no longer operating. Since the CPU clock signals are disabled, the CPU cannot supply a "snoop" result. The ACPI requirements specify that a processor in the C3 state or non-snoopable state be activated to the full-function C0 state in response to a PCI request which typically signifies a request to snoop the CPU cache. Accordingly, under the ACPI specification, a processor in the C3 state responds to a PCI cycle request attempting to access system memory by entering the fully-powered C0 state to allow the cache to be snooped, allowing the snoop, then determining whether to return to the C3 state via software operating in the CPU.
Unfortunately, the act of forcing the CPU from the C3 state into the C0 state is sub-optimal because the C0 state consumes so much power.
What is needed is a circuit and operating technique for conserving power in a computer system such as a portable computer system that is generally compliant with the ACPI specification.